Field
Embodiments relate to the field of processors. In particular, embodiments relate to the field of cache management in multi-core processors.
Background Information
Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be included in processors and other integrated circuit devices. As a result, many processors now have multiple to many cores that are monolithically integrated on a single integrated circuit or die. The multiple cores generally help to allow multiple threads or other workloads to be performed concurrently, which generally helps to increase execution throughput.
However, the multiple cores may have a downside in terms of longer hit and/or miss latencies to a shared cache. Often, the processors have a shared cache that is physically distributed across the integrated circuit or die. For example, cache slices of the distributed cache may be co-located with corresponding cores. Commonly, all of the cores are able to access all of the cache slices. The time for a core to access data from a given cache slice generally depends on the distance between the core and the given cache slice. As a result, as the number of cores on the processor increases, the average distance between cores and cache slices, as well as the average access hit and/or miss latencies, also generally increases. In addition, the multiple or many cores also tend to increase the memory address entropy at memory controllers, which may tend to result in lower effective memory bandwidth.